IRT Nanoelec presented its 3DNOC circuit, the second demonstrator chip to be produced under the IRT Nanoelec 3D Integration program, at the 2016 IEEE International Solid-State Circuits Conference held in San Francisco from February 1–4, 2016. The event was attended by 2,900 people.
IRT Nanoelec’s 3DNOC circuit is a logic-on-logic chip made up of a 3D stack of two identical circuits, each of which is a heterogeneous MPSoC (Multi-Processor System-on-Chip) comprising an ARM1176 core, signal processors, hardware accelerators, and heat probes. The robust asynchronous-logic architecture will target 3GPP-LTE telecoms applications. The circuit also has built-in 3D testability and fault-tolerance mechanisms. In terms of the technology, the 70 mm² circuit was fabricated on the STMicroelectronics 65 nm CMOS line using 3D technology developed under the IRT Nanoelec 3D Integration program (TSV middle with a 10 µm diameter and 40 µm pitch; die-to die, face-to-back).
The 3D circuit was verified using 3D design software by Mentor Graphics, a partner of the IRT Nanoelec 3D Integration program. The 3D asynchronous communication links offer transmission speeds of 326 Mbit/s and energy efficiency of 0.66 pJ/bit: the best performance ever achieved by this type of 3D circuit and a substantial leap ahead of the previous state of the art.
A demonstration of the chip was given at the conference to show the adaptability of 3D communication link performance to circuit temperature, a critical effect of this type of 3D circuit. The 3DNOC concept—a complex 3D system with a high-level communication protocol—will be of interest to businesses specializing in servers or networks handling large volumes of data.