With the advent of Industry 4.0 and the era of connectivity, electronic devices use an ever increasing number of components. At a time when Moore’s Law is running out of steam, 3D integration represents an alternative for further developing multifunction chips while reducing overall dimensions. These 3D techniques increase performance (for example, the bandwidth between a processor and the memory), reduce electrical consumption by replacing a long horizontal connection with a short vertical connection, lower production costs by using technology adapted to the desired functionality, and reduce the form factor.
These advantages are of great interest to both academic research groups and the microelectronics industry. In addition, the rapid emergence of this technology in the industry requires a global approach that takes into account both the development of the technology and the design of new 3D circuit architectures, as well as the development of design, testing and reliability tools. For these reasons, 3D integration is a natural part of Nanoelec’s core programs.
Through the use of 3D electronics, it has become possible to transfer processing functions with high added value, such as object recognition or motion capture. On a mobile system, such as a cell phone, the challenge is
to relieve the central processor of computing capacity, energy consumption and heat dissipation. This is how Nanoelec 3D Integration program has gradually shifted towards developing technologies for capturing and interpreting images, with more autonomous and smarter components in mind, while incorporating ever more complex image processing functions.
Another field of application addressed by the partners of the 3D program is high-performance computing, an area for which 3D integration and advanced packaging technologies have gradually become the norm, due to the increasing need for performance. Silicon interposers, first passive and then active, i.e., smart, are now widely deployed in high-performance systems. The 3D program has been a pioneer in this area with the development of smart interposers.
This was demonstrated in 2019 by a number of significant advances reported in the scientific publications presented below. These publications also open up vast scientific and technological fields that will need to be explored to enable manufacturers to incorporate 3D architectures into their processes and products. Many questions arise especially with respect to interfaces, such as mastery of hybrid bonding, conductive channels (vias)
or even interposers.
To mention only certain major advances: since the start of the program in 2012, we have produced two world-class proofs of concept: a 3D-integrated image sensor with a connection pitch of 1.4 μm; and an active interposer
incorporating power supply and power management functions. Both have received high-profile scientific recognition, with publications in IEEE IEDM and IEEE ISSCC.
Another success story of the program is the introduction of a new equipment on the market by the equipment manufacturer SET. This equipment, apart from being an important event for the company with less than 100 employees, is also a major advance for microelectronics. In fact, it is the first equipment of its kind in the world. The success of a project is also measured by its appeal. Started with three partners in 2012, the 3D program had grown to six partners at the end of 2019. Prophesee, a French start-up
specializing in event-based image sensors, and Aledia, specializing in displays, joined the consortium in mid-2019. In 2020, Lynred, global leader in designing and manufacturing IR imaging technologies, also joined the
consortium. On the one hand, they are proof of the relevance of the consortium’s choices with respect to 3D technologies for image capture and, on the other hand, of the generic nature of the technological building blocks to explore new applications that can create high added value for new French start-ups.