The semiconductor industry is looking to 3D integration—creating electronic chips with multiple horizontal and vertical layers of components—to meet the integrated circuit market’s growing demand for more features, density, and performance.
On the fiercely competitive global integrated circuit market, time is of the essence. And a holistic approach to R&D—one that covers technology development, new 3D circuit architectures, design tools, testing, and reliability—is the most efficient way to get economically-competitive 3D integration technologies to integrated circuit makers quickly.
IRT Nanoelec is taking just such an approach.
The purpose of the program is to develop an end-to-end 3D integration lab that addresses the entire manufacturing value chain. The program will also make it easier for businesses to adopt 3D integration through initiatives like “shared wafer” and other multi-project partnerships with businesses outside the program.
- First demonstrator: multi-project assembly. Initial results: multi-project assembly completed and technology bricks validated
- Second demonstrator: logic assembly
- Third demonstrator: first multi-chip assembly on active interposer
> Partners of the consortium ‘3D integration’